Intel reboots Atom microarchitecture with Tremont design

Intel has released its new low-power x86 microprocessor architecture named Tremont, aimed at cheap notebooks, dual-screen and Internet of Things devices, data centre servers and 5G networking equipment.

Tremont follows Intel's Goldmont iteration of the Atom microarchitecture, and is expected to appear in the Lakefield 10 nanometre processor destined for super thin and light ultrabooks such as Microsoft's Surface Neo.

Lakefield is a hybrid design that uses the Foveros 3D-assembly technology to stack four energy-efficient Atom cores with a more powerful Core chip.

The Tremont-based Atom cores will be utilised for less demanding background tasks, and the Core chip for more processor intensive work, similar to current ARM-designed parts that compete with Intel's electronics.

Atom general processor performance has been criticised for being lacking in the past. 

Compared to earlier Atom iterations, Tremont provides substantial instructions per cycle performance improvments, which are needed to make its low-power x86 processsors competitive against AMD's Zen and Zen 2 parts.

With Tremont, Intel is trying to address criticism over lacklustre processing power with new design features that bump up single-thread performance over the existing Goldmont chips with at least 30 per cent.

This is done by borrowing class branch prediction technology from Intel's Core processors, a 6-wide (2 by 3) out-of-order instruction decode unit feeding into a 4-wide allocation part.

Tremont also features ten execution ports, and dual load and store pipelines to increase performance, along with level 2 cache sizes of up to 4.5 megabytes for quad-core modules.

Power consumption for Tremont-based parts is designed to fall between 0.5 to 2 Watts, Intel said.

Security has received an overhaul for Tremont too, with Intel's rooted security boot that uses Trusted Execution Technology and Boot Guard, and fully encrypts data in memory.

"We focused on a range of modern, complex workloads, while considering networking, client, browser and battery so that we could raise performance efficiently across the board," said Intel senior principal engineer Stephen Robinson at the Linley Falls processor conference in Santa Clara, California.